Pulse width modulation (PWM) is a straightforward and cheap (subsequently widespread!) solution to implement reasonable efficiency (e.g., 8 bit decision low velocity) digital to analog conversion, however improvising low cost DACs isn’t the one factor PWM can do. For instance, Determine 1’s circuit illustrates utilizing PWM to digitally set the analog achieve of a flexible, sturdy, excessive (1 MΩ) enter impedance, buffered output, DC enter stage over a ~16 bit = 65280:1 = -48 dB to +48 dB attenuation/achieve vary.
Determine 1 A PWM managed amplifier/attenuator DC enter stage.
Right here’s the way it works: A 1 MHz, 8 bit (T = 256 µs interval) PWM management sign runs three synchronous HC4053 SPDT CMOS switches designated U1a, U1b, and U1c. Its responsibility cycle = G/T = 0.4% to 99.6% as G = 1 to 255 µs.
U1b acts as a programmable enter attenuator by steering the I = Vin/R1 enter present alternately to floor or op-amp A1’s summing level, creating an enter scale issue of Vin/R1(G/T) that’s programmable between close to zero, Vin/R1/256 (G = 1 µs), to close unity, Vin/R1/255/256 (G = 255 µs). Moreover, due to the near-zero summing-point-potential maintained at U1 pin15 by present steering, the accommodated Vin voltage vary could be very broad—restricted largely by R1’s axial voltage face up to functionality which is usually 200 V for a ¼ W axial lead 1 MΩ resistor. Concurrently, the millivolt vary sign ranges maintained throughout U1b’s change parts (a number of orders of magnitude lower than datasheet take a look at situations) scale back change associated leakage currents to << 1 nA; thus, minimizing leakage-related offset voltages to negligible ranges regardless of the megohm R1.
In the meantime, U1a is working to selectively steer present suggestions from A1’s output to its summing level through R2 with a programmable issue of (1 – G/T), yielding a web V/I achieve of
–R2/ (1 – G/T), whereas sustaining comparable leakage-minimizing millivolt voltage differentials throughout U1a’s switches.
The web impact makes A1’s voltage achieve = -(R2/R1)(G/T)/(1 – G/T) = -(G/T)/(1 – G/T).
As G varies from 1 µs to 255 µs, there’s the acknowledged –(1/256)/(1 – 1/256) to -(255/256)/(1 – 255/256) = -1/255 to -256 = 96 dB achieve vary, however what about that pesky minus signal and notorious PWM ripple?
Each sign inversion and ripple-suppression are carried out by the pattern and maintain operate carried out by U1c and A2, yielding a ultimate ripple-free: Vout/Vin = (G/T)/(1 – GT) as graphed linearly in Determine 2 and logarithmically in Determine 3.
Determine 2 The linear achieve plot (Purple = 0 to five and Blue = 0 to 255).
Determine 3 The log achieve plot.
The constructive (Vdd) and damaging (Vee) energy rails are non-critical and noise-insensitive however ideally ought to be a minimum of roughly symmetrical and can sometimes be +5 V and -5 V, respectively. Whole present draw is lower than 2 mA. Each C1 and C3 ought to be low-leakage sorts, polystyrene is recommended. Response time to an enter or achieve set step is considerably achieve dependent however is usually ~2 ms. Observe that the R1C1 time fixed is ~4T = 1 ms. Neither is strictly what you’d name lightning quick, however we’re in any case speaking about PWM!
Stephen Woodward’s relationship with EDN’s DI column goes again fairly a methods. In all, a complete of 64 submissions have been accepted since his first contribution was printed in 1974.
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